The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, which allows more components to be integrated into a given area. However, the smaller feature size may lead to more leakage current. As the demand for even smaller electronic devices has grown recently, there has grown a need for reducing leakage current of semiconductor devices.
In a metal oxide semiconductor (MOS) field effect transistor (FET), active regions include a drain, a source, a channel region connected between the drain and the source, and a gate to control the on and off state of the channel region. When the gate voltage is more than a threshold voltage, a conductive channel is established between the drain and the source. As a result, electrons or holes are allowed to move between the drain and source. On the other hand, when the gate voltage is less than the threshold voltage, ideally, the channel is cut off and there are no electrons or holes flowing between the drain and the source.
As semiconductor devices keep shrinking, due to the short channel leakage effect, the gate cannot fully control the channel region, especially the portion of the channel region which is far away from the gate. As a consequence, after semiconductor devices are scaled into deep sub-30 nanometer dimensions, the corresponding short gate length of conventional planar transistors may lead to the inability of the gate to substantially turn off the channel region.
As semiconductor technologies evolve, multigate devices such as fin field effect transistors (FinFETs), trigate FETS, pi-gate or omega-gate FETs, gate-all-around (GAA) FETs and nanowire FETs have emerged as an effective alternative to further reduce leakage current in semiconductor devices. We will here use the word “FinFET” to describe multigate FETs in general. In a FinFET, an active region including a drain region, a channel region and a source region protrudes up from the surface of the semiconductor substrate upon which the FinFET is located. The active region of the FinFET, like a fin, is rectangular, trapezoidal or triangular in shape from a cross section view. In addition, the gate structure of the FinFET wraps the active region around three sides like an upside-down U. As a result, the gate structure's control of the channel has become stronger. The short channel leakage effect of conventional planar transistors has been reduced. As such, when the FinFET is turned off, the gate structure can better control the channel so as to reduce leakage current.
As semiconductor technologies further evolve, high speed integrated circuits are needed to maintain the electronic components' performance from one generation to the next. For example, semiconductor transistors formed by high carrier mobility materials such as III-V materials, germanium and/or the like are desirable for high density and high speed integrated circuits.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the various embodiments and are not necessarily drawn to scale.